μCOM-87: The Strangest Architecture You've Never Worked With - ajxs.me
If you've stumbled across this page looking for practical information on how to work with NEC's μCOM-87 architecture<br>today, skip straight to this section.
With most of the<br>DX7's<br>technical mysteries laid bare (for now), I've had some free time to poke around inside another 80s digital synth icon: the<br>Casio CZ-101.
In 1983, Yamaha changed the music world forever with the release of the DX7. It used a new synthesis technique called<br>FM synthesis<br>to create a bold, futuristic sound that was radically different from everything else available. It wasn't just a commercial success; The DX7 was a tectonic shift that reshaped the<br>entire landscape of popular music, and left Yamaha's competitors scrambling to get in on the action. The theory behind FM synthesis was simple, but Yamaha held the patent and were fiercely<br>protective of their advantage. It would take Korg and Roland years to bring their own competitors to market, but Casio —a comparatively small player in the synth market—<br>managed to thread the needle with the CZ-101's Phase Distortion Synthesis. If you closed your eyes you could almost pretend someone had shrunk a DX7. It had plucky basses, resonant bells, gritty metallic percussion... All without running afoul of the<br>notoriously litigious Yamaha's FM patents. The CZ-101 was a lot of fun squeezed into a small package. It<br>sold well, and still enjoys a cult status today.
Under the hood, the CZ-101 uses several NEC chips: The proprietary<br>μPD933 tone generator 1, and the μPD7811G microcontroller. Unsurprisingly, no public documentation exists for the μPD933, and —despite having once been a commercial product— the<br>situation for the μPD7811G isn't much better. When I started<br>poking around<br>in the firmware ROM, I struggled to find good resources online about the<br>μCOM-87 architecture used in the μPD7811G... Despite appearing in some really important places there's surprisingly little written about it online. For that reason I<br>decided to write my own account of its more baroque features.
In case anyone is interested, my (incomplete) disassembly of the CZ-101's v2 firmware ROM can be found<br>here.
Background #
The NEC μPD7810G CPU. Image courtesy of<br>CPU Graveyard.
In 1978 Japanese mega-corporation NEC<br>2 launched their first original 8-bit processor architecture: The μCOM-87. Until this point, NEC's<br>8-bit architectures<br>had all been based on existing designs, such as the<br>Intel 8080-compatible μCOM-8, and<br>Zilog Z80-compatible μCOM-82.
NEC had clearly learned a few things from their American counterparts: The<br>μCOM-87 architecture featured two parallel banks of 8080-like registers, which could be swapped between like in the similar Z80. The 8-bit<br>B and C registers can also be 'paired' into a single 16-bit register (BC).<br>Same with DE, and HL, similar to the 8080 and Z80 architectures.
NEC μCOM-87 Register Set.
Now I know what you're thinking:<br>Yeah, yeah. 8080-compatible registers, register pairing, alternate banks... This is all pretty normal 8-bit stuff.<br>Sure... But those are just about the only normal things about the μCOM-87 architecture. Let's take a look at a few of its more exotic features...
Instruction Skipping #
Note:<br>The assembly examples in this article follow<br>Intel's<br>format for hexadecimal literals, which is also used by NEC in their 87AD series relocatable assembler (RA87).<br>i.e. 0ABCDh, rather than 0xABCD.
Instead of conventional<br>comparing and branching instructions, control flow on the μCOM-87 works by conditionally skipping instructions.
; Read a byte from the serial interface into A.<br>; Clamp the value between 0xA - 0xF, then send back.<br>MOV A,RXB
; Skip the next instruction if A<br>LTI A,010h<br>; Clamp A at 0xF.<br>MVI A,0Fh
; Skip the next instruction if A > 0xA.<br>GTI A,0Ah<br>; Clamp A at 0xA.<br>MVI A,0Ah
MOV TXB,A
The above example reads a value from the serial interface, and clamps it between 0xA and 0xF. The LTI (Less Than<br>Immediate) instruction skips the next instruction if the register is less than the immediate operand. Similarly, the GTI instruction skips if the<br>register is higher than the immediate operand.
Instruction skipping is practically unheard of in modern architectures, but featured in a few other historic ones like the<br>PDP-8, and
Microchip's PIC<br>architectures prior to PIC18.
The following table lists most of the μCOM-87's instructions which can trigger the next instruction to be skipped. Some nearly identical instructions have been omitted for<br>brevity 3.
μCOM-87's Skipping Instructions
Instruction<br>Description<br>Skip Condition
ADDNC r, A<br>Add A to Register. Skip if No Carry<br>No carry generated
ADDNCX rpa<br>Add Memory addressed by Register Pair to A. Skip if No Carry<br>No carry generated
BIT bit, wa<br>Bit Test Working Register<br>V.wa[bit] != 0
DADDNC EA, rp3<br>Add Register Pair to EA. Skip if no Carry<br>No carry generated
DEQ EA, rp3<br>Equal Register Pair with EA<br>EA == rp3
DGT EA, rp3<br>Greater Than Register Pair<br>EA > rp3
EQA...