Revela ISP — an image signal processor written in NumPy
Revela ISP™
An image signal processor written in NumPy, compiled to<br>bit-exact hardware.
Camera to screen, entirely in fabric. A Raspberry Pi<br>camera's raw Bayer travels over HDMI to a PYNQ-Z2; black level, white<br>balance, an adaptive Hamilton-Adams demosaic, a colour matrix and gamma<br>all run in the FPGA at 1920×1080, 10-bit, 148.5 MHz on one clock. The<br>mark in the corner is drawn by the pipeline itself.
Every block is a Python function using NumPy. That model is the<br>specification, the simulator, and the source the Verilog is generated<br>from — and the generated hardware is checked bit-exact against the model<br>before it is allowed to emit. There is no hand-written Verilog anywhere<br>in it.
The model is the hardware. Not a reference the<br>RTL is compared against afterwards — the one description, from which the<br>RTL is produced and against which it must agree, or nothing ships.
Nor are the pipeline registers placed by hand. You give the compiler a<br>clock and it works out, from the expression graph, how deep each stage can<br>be, then puts the registers where they have to go. When something genuinely<br>cannot fit it refuses at generation time and names the operation — in<br>microseconds, rather than after a place-and-route that names a net.
Why this matters
Verification is where hardware time really goes, and everyone who has<br>shipped RTL knows it. For an ASIC a missed bug is not a bad demo, it is a<br>respin. Revela is generated with a FuseSoC generator, so the pipeline is<br>a building block for a chip: you can already build one from open RISC-V<br>cores, and the image pipeline can now come from the same place.
This is the start. The blocks in the video are the ones everybody<br>starts with, and a long queue of image processing patents is going<br>through expiration right now — Hamilton-Adams is in this demo because<br>its patents expired, and more come free over the next couple of years.
Writing
How Revela ISP started Twelve years of image processing<br>algorithms, a compiler idea shelved in 2011, and what brought it<br>back.14 August 2026
All writing →
The pieces
revela The ISP: blocks as NumPy functions, a JSON<br>pipeline netlist, run-time parameters, a generated register map.
np2hw The compiler: NumPy to line-based Verilog, bit-exact,<br>with pipeline stages placed from a traced depth model.
bayerlink Raw Bayer over HDMI, so any Raspberry Pi sensor<br>reaches any FPGA board with an HDMI input.
picam2hdmi The Raspberry Pi side, with web controls for<br>source, geometry and exposure.
bayerlink-fpga The board design the video was recorded<br>from: receiver, ISP and display raster, all generated.
Try it
pip install revela np2hw bayerlink<br>The demo runs on a PYNQ-Z2 and a Raspberry Pi camera. The board design,<br>the build script and the measurements are in<br>bayerlink-fpga.
Talk to me
I am looking for people who will use this. If you are building a camera<br>pipeline and the ISP is in your way, write to<br>s.rabykin@gmail.com. Support the<br>work at GitHub<br>Sponsors.